1. Field of the Invention
Embodiments of the invention relate to non-volatile storage using resistance elements, in particular, using phase change memory elements (PCM).
2. Description of the Related Art
Memory cells may be used in all applications which use data storage. Typical semiconductor circuits comprise data memory cells which are either formed between logic elements, such as, e.g., latch registers, or which are formed as block memories, such as SRAM (static random access memory), for example. A block memory typically comprises an array of memory cells, only a few cells being subjected to a write operation or a read-out operation simultaneously. Therefore, the columns of a block memory array may have common area-consuming elements, such as, e.g., sense amplifiers, which support the storage or read-out operation. On the other hand, in the case of distributed data memory cells, which are, e.g., part of a logic circuit, these cells may permanently supply the stored information if the cell is continuously read.
There are a multiplicity of implementations of volatile memory cells, in the case of which the stored information is lost when the supply power is turned off, and of non-volatile memory cells. FIGS. 9a to 9c illustrate some memory cells known from the prior art, FIG. 9a showing a 6T-SRAM cell, FIG. 9b showing a flash cell, and FIG. 9c showing a latch cell.
What may be disadvantageous about the SRAM cells and the latch cells may be that they are volatile and have a considerable area usage. Flash technology may use a second, high supply voltage (12 V-18 V), the generation of which may use voltage pumps which take up area and cause, e.g., crosstalk. Flash technology is furthermore distinguished by an only limited scaling potential and permits only a limited number of write cycles.
Modern memory technologies typically comprise large memory modules based on resistance elements, such as, e.g., ferroelectric random access memories (RAMs), magnetoresistive RAMs, or phase change RAMs. However, these architectures are usually aimed at the array-based block memories mentioned above, only a few cells being read simultaneously.
A promising technology for memory circuits is the phase change memory (PCM) technology already mentioned, the characteristic of which comes close to the characteristic of preprogrammable resistance elements R1 and R2. The fundamental principle of PCM elements is based on a thermally engendered reversible phase change between an amorphous phase and a crystalline (e.g. polycrystalline) phase of a chalcogenide glass.
The amorphous state produces a high resistance, whereas the polycrystalline state produces a low resistance. The phase change is engendered by heat which arises on account of a current flow through the resistance element. The duration and the intensity of the current determine whether the element subsequently has a high or a low resistance value. Phase change technology is currently the subject of intensive research with regard to its use in particular in block memories. Typical values for phase change elements are a reset current (on to off) of 200 μA over 10 ns and a subsequent resistance value Roff in the region of 1 MΩ, and a set current (off to on) of approximately 50 μA with a duration of 50 ns, which results in a subsequent resistance value Ron in the region of 10 kΩ.
Non-volatile memory cells which use programmable resistance elements are known from the prior art. US 2004/0125643 A1 discloses a non-volatile memory cell illustrated in FIG. 10. The circuit comprises a write/read controller (20), two programmable resistance elements (R1 and R2) and also a switch (SW2). The resistance elements are programmed on the basis of PCM technology. During the write operation, as a result of a choice of the suitable polarities of the control signals WRC1, WRC2 and WRC3, a current is constrained through the resistance elements R1 and/or R2, as a result of which they are programmed. During the read-out operation, as a result of an application of a low WRC2 (WRC2=low) and a high WRC3 (WRC3=high), a transmission gate (20) is converted into a non-conducting state, so that a voltage level is established at the node F, in a manner dependent on the states of the resistance elements and the nodes D and E, which voltage level controls the switch SW2.
What may be disadvantageous about the above concept may be inflexibility in the write operation. PCM elements are typically programmed into the high-resistance state using a current having a high amplitude for a short time duration and into the low-resistance state using a lower current for a longer time duration. For this purpose, different voltages have to be generated across R1 and R2, so that the amplitudes of the currents through the resistance elements are generated by a difference between the voltages across the resistance elements. Consequently, the amplitudes of the currents depend on one another, so that it is not possible for them to be set precisely and individually. Furthermore, different voltages have to be generated across the resistance elements, which is associated with a high outlay. High losses (leakage) furthermore arise because the PCM elements attain a resistance value in the region of 1 MΩ in the high-resistance state. If a voltage of approximately 1 V were applied between the nodes D and E, then a cross current of approximately 1 μA would flow. Such a current loss (leakage current) may be unacceptable for some applications. A further possible disadvantage of the above concept may be that there is a risk of a destructive read-out during the read-out of the memory cells. A current which flows through R1 and R2 for the purpose of reading out the stored information might erase the stored information in the case of an imprecise setting.
US 2004/0141363 A1 discloses a non-volatile flip-flop. The basic circuit is illustrated in FIG. 11a. This involves a conventional SRAM cell that has been extended by a pass transistor (9, 10) and by a resistance element (11, 12), which connects a metallization (plate line, PL) to each of the inverters (5, 6). The bit lines (BL1, BL2) are connected to the cross-coupled inverters via transistors (7, 8). A timing diagram illustrated in FIG. 11b shows an example of a write operation in which the two resistance elements are initially reset by means of a suitable pulse sequence of the signals “CL” and “PL”. Afterwards, one of the two resistance elements is set into a state having a low resistance by means of a short pulse on the common control signal line (CL). Which of the two elements is converted (set) into the low-resistance state depends on the state of the nodes 5 and 6. As illustrated in FIG. 11b, the reset operation or the set operation may differ either in terms of a pulse length or in terms of the applied voltage.
FIG. 11d illustrates a timing diagram in the case of a read operation, a pulse being applied to the “CL” line, while a potential of the “PL” line is increased in ramped fashion in the direction of the full supply voltage. The nodes 5 and 6 are charged at different speeds depending on the resistance of the PCM elements. During the ramped increase in the potential of the “PL” line, the supply voltage for the inverters is switched on, so that the inverters output the output signals in accordance with the precharged nodes 5 and 6.
What may be disadvantageous about the above cell is that the read-out may be susceptible to errors. What may furthermore be disadvantageous is that a destructive read out of the PCM elements involving the erasure of the stored information during read-out may, in some cases, only be prevented by means of a precise voltage ramp on the “PL” line. This may increase the production costs because components having smaller tolerances may have to be provided for this purpose. Moreover, on account of the precise control which may be used in order to avoid the read-out errors, the control outlay may be increased, which may entail an increase in complexity. Furthermore, the n MOS pass transistors may not be able to transmit the full voltage swing, whereby an error-free execution of the write operation may be prevented in the case of the PCM elements. The write operation may furthermore be inflexible because either the pulse length is changed for the set/reset operation (more precise specifications made of the PCM technology) or a second supply voltage may be used, which may be associated with additional costs.
A further possible disadvantage of the known cell may be that after the supply voltage has been switched off, the sequence of the precisely highly ramped “PL” signal synchronized with a distinct ramp of the total supply voltage, and a pulse of the “CL” signal may use a high outlay in order to ensure a robust reestablishment of the correct values, and in order to prevent a destructive read-out.
The prior art, e.g. US 2004/0141363 A1, discloses writing mechanisms in which a high or a low resistance state is stored (that is to say, written) in the programmable PCM element either by changing a duration of a width of a programming current pulse, as illustrated in FIG. 12a, or by applying a higher voltage, as illustrated in FIG. 4b. What may be disadvantageous in this case is that exclusively changing the current pulse width may make requirements of PCM technology which are currently not met by most PCM process technologies. The provision of different voltage levels may not be expedient either. In many applications, there may be no second suitable voltage supply on the chip. Generation and distribution of a second voltage by means of a charge pump are associated with an additional area consumption and thus with additional costs. Furthermore, deriving a voltage having a low voltage value from a voltage having a higher voltage value causes not only a control outlay (overhead) but also problems on account of a reduced signal swing.